As a method for forming a gate electrode of a MISFET in a semiconductor device, there is a dry etching method using a resist pattern as an etching mask. The dry etching method is a technique for making process gas introduced in a vacuum case become plasma utilizing high-frequency power applied externally to cause reactive radical or ion produced in the plasma to react on a wafer at high precision, thereby selectively processing a silicon film which is a film to be processed on mask material or a gate insulating film as typified by resist.
Japanese Patent Application Laid-Open Publication No. 2002-289592 (Patent Document 1) describes a technique where a constitution for etching and removing a antireflection film of an opening portion of resist using etching gas containing halogen substitution of carbon hydride as component is adopted, so that when the antireflection film is etched, carbon component in the halogen substitution of carbon hydride is formed as carbonaceous deposit on sidewalls of the opening portion of the resist which is subjected to reduced ion irradiation and sidewalls of an opening portion which is formed according to the etching of the antireflection film, and the deposit serves as a sidewall passivation film, so that lateral spreading of the opening portion of the resist and the opening portion of the antireflection film due to etching is suppressed, thereby enabling anisotropic etching of the antireflection film.
Japanese Patent Application Laid-Open Publication No. 2000-164571 (Patent Document 2) describes a technique regarding a contact hole forming method including a step of forming an insulating film (an interlayer insulating film) on a conductive layer (a semiconductor substrate), a step of forming a resist film on the insulating film, a step of performing exposure and development of the resist film for providing an opening in the resist film, a step of performing a first etching utilizing the resist film as a mask to remove at least a portion of the insulating film while depositing reaction product of etching gas on the resist film surface, and a step of performing a second etching different in etching condition from the first etching to open a contact hole reaching the conductive layer.
Japanese Patent Application Laid-Open Publication No. 10-4084 (Patent Document 3) describes a technique for achieving etching excellent in anisotropy by, after forming a resist film on a metal film on a substrate in a first step, patterning the resist film by lithography technique to form a resist pattern, and after forming a passivation film on a surface of the resist pattern by plasma process using gas of fluorocarbon based in a second step, etching the metal film using the resist pattern on which the passivation film has been formed as an etching mask in a third step.
Japanese Patent Application Laid-Open Publication No. 11-195641 describes a technique of alternately performing an etching step using SF6 gas and a deposition step using C4F8 plural times to form a deep groove in silicon by high-rate etching using silicon oxide as a mask.
Patent Document 1: Japanese Patent Application Laid-Open Publication No. 2002-289592
Patent Document 2: Japanese Patent Application Laid-Open Publication No. 2000-164571
Patent Document 3: Japanese Patent Application Laid-Open Publication No. 10-4084
Patent Document 4: Japanese Patent Application Laid-Open Publication No. 11-195641